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Artikel ini berisi jawaban dari soal-soal Review Questions dalam e-book "COMPUTER ORGANIZATION AND ARCHITECTURE DESIGNING FOR PERFORMANCE EIGHT EDITION" by WILLIAM STALLINGS. Dulunya ini udah menjadi tugas kuliah gw (kelas COA), tapi dulu mencari jawaban soalnya harus di search satu/satu di google, jadinya susah and wasted my time :D makanya gw udah kemas jawabannya dalam artikel ini :)
Last,,semoga ini bisa membantu teman-teman khususnya di Computer Science Faculty dalam mengerjakan tugas kuliah-nya (COA).
SOLUTIONS MANUAL COMPUTER ORGANIZATION AND ARCHITECTURE
DESIGNING FOR PERFORMANCE
EIGHT EDITION
WILLIAM STALLINGS
Answer Key Chp. 2 : COMPUTER EVOLUTION AND
PERFORMANCE
2.1 In a stored program computer, programs are represented in a form suitable for
storing in memory alongside the data. The computer gets its instructions by reading
them from memory, and a program can be set or altered by setting the values of a
portion of memory.
2.2 A main memory, which stores both data and instructions: an arithmetic and logic
unit (ALU) capable of operating on binary data; a control unit, which interprets the
instructions in memory and causes them to be executed; and input and output
(I/O) equipment operated by the control unit.
2.3 Gates, memory cells, and interconnections among gates and memory cells.
2.4 Moore observed that the number of transistors that could be put on a single chip
was doubling every year and correctly predicted that this pace would continue into
the near future.
2.5 Similar or identical instruction set: In many cases, the same set of machine
instructions is supported on all members of the family. Thus, a program that
executes on one machine will also execute on any other. Similar or identical
operating system: The same basic operating system is available for all family
members. Increasing speed: The rate of instruction execution increases in going
from lower to higher family members. Increasing Number of I/O ports: In going
from lower to higher family members. Increasing memory size: In going from
lower to higher family members. Increasing cost: In going from lower to higher
family members.
2.6 In a microprocessor, all of the components of the CPU are on a single chip.
Answer Key Chp. 3 : COMPUTER FUNCTION AND
INTERCONNECTION
3.1 Processor-memory: Data may be transferred from processor to memory or from
memory to processor.
Processor-I/O: Data may be transferred to or from a
peripheral device by transferring between the processor and an I/O module.
Data processing: The processor may perform some arithmetic or logic operation on data.
Control: An instruction may specify that the sequence of execution be altered.
3.2 Instruction address calculation (iac): Determine the address of the next instruction
to be executed.
Instruction fetch (if): Read instruction from its memory location
into the processor. Instruction operation decoding (iod): Analyze instruction to
determine type of operation to be performed and operand(s) to be used. Operand
address calculation (oac): If the operation involves reference to an operand in
memory or available via I/O, then determine the address of the operand.
Operand fetch (of): Fetch the operand from memory or read it in from I/O.
Data operation (do): Perform the operation indicated in the instruction.
Operand store (os): Write the result into memory or out to I/O.
3.3 (1) Disable all interrupts while an interrupt is being processed.
(2) Define priorities
for interrupts and to allow an interrupt of higher priority to cause a lower-priority
interrupt handler to be interrupted.
3.4 Memory to processor: The processor reads an instruction or a unit of data from
memory. Processor to memory: The processor writes a unit of data to memory. I/O
to processor: The processor reads data from an I/O device via an I/O module.
Processor to I/O: The processor sends data to the I/O device. I/O to or from
memory: For these two cases, an I/O module is allowed to exchange data directly
with memory, without going through the processor, using direct memory access
(DMA).
3.5 With multiple buses, there are fewer devices per bus. This (1) reduces propagation
delay, because each bus can be shorter, and (2) reduces bottleneck effects.
3.6 System pins: Include the clock and reset pins. Address and data pins: Include 32
lines that are time multiplexed for addresses and data. Interface control pins:
Control the timing of transactions and provide coordination among initiators and
targets. Arbitration pins: Unlike the other PCI signal lines, these are not shared
lines. Rather, each PCI master has its own pair of arbitration lines that connect it
directly to the PCI bus arbiter. Error Reporting pins: Used to report parity and
other errors. Interrupt Pins: These are provided for PCI devices that must generate
requests for service. Cache support pins: These pins are needed to support a
memory on PCI that can be cached in the processor or another device. 64-bit Bus
extension pins: Include 32 lines that are time multiplexed for addresses and data
and that are combined with the mandatory address/data lines to form a 64-bit
address/data bus. JTAG/Boundary Scan Pins: These signal lines support testing
procedures defined in IEEE Standard 1149.1.
Answer Key Chp. 4 :CACHE MEMORY
4.1 Sequential access: Memory is organized into units of data, called records. Access
must be made in a specific linear sequence. Direct access: Individual blocks or
records have a unique address based on physical location. Access is accomplished
by direct access to reach a general vicinity plus sequential searching, counting, or
waiting to reach the final location. Random access: Each addressable location in
memory has a unique, physically wired-in addressing mechanism. The time to
access a given location is independent of the sequence of prior accesses and is
constant.
4.2 Faster access time, greater cost per bit; greater capacity, smaller cost per bit; greater
capacity, slower access time.
4.3 It is possible to organize data across a memory hierarchy such that the percentage
of accesses to each successively lower level is substantially less than that of the level
above. Because memory references tend to cluster, the data in the higher-level
memory need not change very often to satisfy memory access requests.
4.4 In a cache system, direct mapping maps each block of main memory into only one
possible cache line. Associative mapping permits each main memory block to be
loaded into any line of the cache. In set-associative mapping, the cache is divided
into a number of sets of cache lines; each main memory block can be mapped into
any line in a particular set.
4.5 One field identifies a unique word or byte within a block of main memory. The
remaining two fields specify one of the blocks of main memory. These two fields
are a line field, which identifies one of the lines of the cache, and a tag field, which
identifies one of the blocks that can fit into that line.
4.6 A tag field uniquely identifies a block of main memory. A word field identifies a
unique word or byte within a block of main memory.
4.7 One field identifies a unique word or byte within a block of main memory. The
remaining two fields specify one of the blocks of main memory. These two fields
are a set field, which identifies one of the sets of the cache, and a tag field, which
identifies one of the blocks that can fit into that set.
4.8 Spatial locality refers to the tendency of execution to involve a number of memory
locations that are clustered. Temporal locality refers to the tendency for a processor
to access memory locations that have been used recently.
4.9 Spatial locality is generally exploited by using larger cache blocks and by
incorporating prefetching mechanisms (fetching items of anticipated use) into the
cache control logic. Temporal locality is exploited by keeping recently used
instruction and data values in cache memory and by exploiting a cache hierarchy.
Answer Key Chp. 5 : INTERNAL MEMORY
5.1 They exhibit two stable (or semistable) states, which can be used to represent binary
1 and 0; they are capable of being written into (at least once), to set the state; they
are capable of being read to sense the state.
5.2 (1) A memory in which individual words of memory are directly accessed through
wired-in addressing logic. (2) Semiconductor main memory in which it is possible
both to read data from the memory and to write new data into the memory easily
and rapidly.
5.3 SRAM is used for cache memory (both on and off chip), and DRAM is used for
main memory.
5.4 SRAMs generally have faster access times than DRAMs. DRAMS are less expensive
and smaller than SRAMs.
5.5 A DRAM cell is essentially an analog device using a capacitor; the capacitor can
store any charge value within a range; a threshold value determines whether the
charge is interpreted as 1 or 0. A SRAM cell is a digital device, in which binary
values are stored using traditional flip-flop logic-gate configurations.
5.6 Microprogrammed control unit memory; library subroutines for frequently wanted
functions; system programs; function tables.
5.7 EPROM is read and written electrically; before a write operation, all the storage
cells must be erased to the same initial state by exposure of the packaged chip to
ultraviolet radiation. Erasure is performed by shining an intense ultraviolet light
through a window that is designed into the memory chip. EEPROM is a readmostly
memory that can be written into at any time without erasing prior contents;
only the byte or bytes addressed are updated. Flash memory is intermediate
between EPROM and EEPROM in both cost and functionality. Like EEPROM, flash
memory uses an electrical erasing technology. An entire flash memory can be
erased in one or a few seconds, which is much faster than EPROM. In addition, it is
possible to erase just blocks of memory rather than an entire chip. However, flash
memory does not provide byte-level erasure. Like EPROM, flash memory uses only
one transistor per bit, and so achieves the high density (compared with EEPROM)
of EPROM.
5.8 A0 - A1 = address lines:. CAS = column address select:. D1 - D4 = data lines. NC: =
no connect. OE: output enable. RAS = row address select:. Vcc: = voltage source.
Vss: = ground. WE: write enable.
5.9 A bit appended to an array of binary digits to make the sum of all the binary digits,
including the parity bit, always odd (odd parity) or always even (even parity).
5.10 A syndrome is created by the XOR of the code in a word with a calculated version
of that code. Each bit of the syndrome is 0 or 1 according to if there is or is not a
match in that bit position for the two inputs. If the syndrome contains all 0s, no
error has been detected. If the syndrome contains one and only one bit set to 1,
then an error has occurred in one of the 4 check bits. No correction is needed. If the
syndrome contains more than one bit set to 1, then the numerical value of the
syndrome indicates the position of the data bit in error. This data bit is inverted for
correction.
5.11 Unlike the traditional DRAM, which is asynchronous, the SDRAM exchanges data
with the processor synchronized to an external clock signal and running at the full
speed of the processor/memory bus without imposing wait states.
Answer Key Chp.6 : EXTERNAL MEMORY
6.1 Improvement in the uniformity of the magnetic film surface to increase disk
reliability. A significant reduction in overall surface defects to help reduce
read/write errors. Ability to support lower fly heights (described subsequently).
Better stiffness to reduce disk dynamics. Greater ability to withstand shock and
damage
6.2 The write mechanism is based on the fact that electricity flowing through a coil
produces a magnetic field. Pulses are sent to the write head, and magnetic patterns
are recorded on the surface below, with different patterns for positive and negative
currents. An electric current in the wire induces a magnetic field across the gap,
which in turn magnetizes a small area of the recording medium. Reversing the
direction of the current reverses the direction of the magnetization on the recording
medium.
6.3 The read head consists of a partially shielded magnetoresistive (MR) sensor. The
MR material has an electrical resistance that depends on the direction of the
magnetization of the medium moving under it. By passing a current through the
MR sensor, resistance changes are detected as voltage signals.
6.4 For the constant angular velocity (CAV) system, the number of bits per track is
constant. An increase in density is achieved with multiple zoned recording, in
which the surface is divided into a number of zones, with zones farther from the
center containing more bits than zones closer to the center.
6.5 On a magnetic disk. data is organized on the platter in a concentric set of rings,
called tracks. Data are transferred to and from the disk in sectors. For a disk with
multiple platters, the set of all the tracks in the same relative position on the platter
is referred to as a cylinder.
6.6 512 bytes.
6.7 On a movable-head system, the time it takes to position the head at the track is
known as seek time. Once the track is selected, the disk controller waits until the
appropriate sector rotates to line up with the head. The time it takes for the
beginning of the sector to reach the head is known as rotational delay. The sum of
the seek time, if any, and the rotational delay equals the access time, which is the
time it takes to get into position to read or write. Once the head is in position, the
read or write operation is then performed as the sector moves under the head; this
is the data transfer portion of the operation and the time for the transfer is the
transfer time.
6.8 1. RAID is a set of physical disk drives viewed by the operating system as a single
logical drive. 2. Data are distributed across the physical drives of an array. 3.
Redundant disk capacity is used to store parity information, which guarantees data
recoverability in case of a disk failure.
6.9 0: Non-redundant 1: Mirrored; every disk has a mirror disk containing the same
data. 2: Redundant via Hamming code; an error-correcting code is calculated across
corresponding bits on each data disk, and the bits of the code are stored in the
corresponding bit positions on multiple parity disks. 3: Bit-interleaved parity;
similar to level 2 but instead of an error-correcting code, a simple parity bit is
computed for the set of individual bits in the same position on all of the data disks.
4: Block-interleaved parity; a bit-by-bit parity strip is calculated across
corresponding strips on each data disk, and the parity bits are stored in the
corresponding strip on the parity disk. 5: Block-interleaved distributed parity;
similar to level 4 but distributes the parity strips across all disks. 6: Blockinterleaved
dual distributed parity; two different parity calculations are carried out
and stored in separate blocks on different disks.
6.10 The disk is divided into strips; these strips may be physical blocks, sectors, or some
other unit. The strips are mapped round robin to consecutive array members. A set
of logically consecutive strips that maps exactly one strip to each array member is
referred to as a stripe.
6.11 For RAID level 1, redundancy is achieved by having two identical copies of all
data. For higher levels, redundancy is achieved by the use of error-correcting
codes.
6.12 In a parallel access array, all member disks participate in the execution of every
I/O request. Typically, the spindles of the individual drives are synchronized so
that each disk head is in the same position on each disk at any given time. In an
independent access array, each member disk operates independently, so that
separate I/O requests can be satisfied in parallel.
6.13 For the constant angular velocity (CAV) system, the number of bits per track is
constant. At a constant linear velocity (CLV), the disk rotates more slowly for
accesses near the outer edge than for those near the center. Thus, the capacity of a
track and the rotational delay both increase for positions nearer the outer edge of
the disk.
6.14 1. Bits are packed more closely on a DVD. The spacing between loops of a spiral on
a CD is 1.6 μm and the minimum distance between pits along the spiral is 0.834
μm. The DVD uses a laser with shorter wavelength and achieves a loop spacing of
0.74 μm and a minimum distance between pits of 0.4 μm. The result of these two
improvements is about a seven-fold increase in capacity, to about 4.7 GB. 2. The
DVD employs a second layer of pits and lands on top of the first layer A dual-layer
DVD has a semireflective layer on top of the reflective layer, and by adjusting
focus, the lasers in DVD drives can read each layer separately. This technique
almost doubles the capacity of the disk, to about 8.5 GB. The lower reflectivity of
the second layer limits its storage capacity so that a full doubling is not achieved.
3. The DVD-ROM can be two sided whereas data is recorded on only one side of a
CD. This brings total capacity up to 17 GB.
6.15 The typical recording technique used in serial tapes is referred to as serpentine
recording. In this technique, when data are being recorded, the first set of bits is
recorded along the whole length of the tape. When the end of the tape is reached,
the heads are repositioned to record a new track, and the tape is again recorded on
its whole length, this time in the opposite direction. That process continues, back
and forth, until the tape is full.
Answer Key Chp. 7: INPUT/OUTPUT
7.1 Human readable: Suitable for communicating with the computer user. Machine
readable: Suitable for communicating with equipment. Communication: Suitable
for communicating with remote devices
7.2 The most commonly used text code is the International Reference Alphabet (IRA),
in which each character is represented by a unique 7-bit binary code; thus, 128
different characters can be represented.
7.3 Control and timing. Processor communication. Device communication. Data
buffering. Error detection.
7.4 Programmed I/O: The processor issues an I/O command, on behalf of a process, to
an I/O module; that process then busy-waits for the operation to be completed
before proceeding. Interrupt-driven I/O: The processor issues an I/O command on
behalf of a process, continues to execute subsequent instructions, and is interrupted
by the I/O module when the latter has completed its work. The subsequent
instructions may be in the same process, if it is not necessary for that process to
wait for the completion of the I/O. Otherwise, the process is suspended pending
the interrupt and other work is performed. Direct memory access (DMA): A DMA
module controls the exchange of data between main memory and an I/O module.
The processor sends a request for the transfer of a block of data to the DMA module
and is interrupted only after the entire block has been transferred.
7.5 With memory-mapped I/O, there is a single address space for memory locations
and I/O devices. The processor treats the status and data registers of I/O modules
as memory locations and uses the same machine instructions to access both
memory and I/O devices. With isolated I/O, a command specifies whether the
address refers to a memory location or an I/O device. The full range of addresses
may be available for both.
7.6 Four general categories of techniques are in common use: multiple interrupt lines;
software poll; daisy chain (hardware poll, vectored); bus arbitration (vectored).
7.7 The processor pauses for each bus cycle stolen by the DMA module.
Answer Key Chp. 8: OPERATING SYSTEM SUPPORT
8.1 The operating system (OS) is the software that controls the execution of programs
on a processor and that manages the processor's resources.
8.2 Program creation: The operating system provides a variety of facilities and services,
such as editors and debuggers, to assist the programmer in creating programs.
Program execution: A number of tasks need to be performed to execute a program.
Instructions and data must be loaded into main memory, I/O devices and files
must be initialized, and other resources must be prepared. Access to I/O devices:
Each I/O device requires its own peculiar set of instructions or control signals for
operation. Controlled access to files: In the case of files, control must include an
understanding of not only the nature of the I/O device (disk drive, tape drive) but
also the file format on the storage medium. System access: In the case of a shared or
public system, the operating system controls access to the system as a whole and to
specific system resources. Error detection and response: A variety of errors can
occur while a computer system is running. Accounting: A good operating system
will collect usage statistics for various resources and monitor performance
parameters such as response time.
8.3 Long-term scheduling: The decision to add to the pool of processes to be executed.
Medium-term scheduling: The decision to add to the number of processes that are
partially or fully in main memory. Short-term scheduling: The decision as to which
available process will be executed by the processor
8.4 A process is a program in execution, together with all the state information
required for execution.
8.5 The purpose of swapping is to provide for efficient use of main memory for process
execution.
8.6 Addresses must be dynamic in the sense that absolute addresses are only resolved
during loading or execution.
8.7 No, if virtual memory is used.
8.8 No.
8.9 No.
8.10 The TLB is a cache that contains those page table entries that have been most
recently used. Its purpose is to avoid, most of the time, having to go to disk to
retrieve a page table entry.
Answer Key Chp. 9: COMPUTER ARITHMETIC
9.1 Sign–Magnitude Representation: In an N-bit word, the left-most bit is the sign (0 =
positive, 1 = negative) and the remaining N – 1 bits comprise the magnitude of the
number. Twos Complement Representation: A positive integer is represented as in
sign magnitude. A negative number is represented by taking the Boolean
complement of each bit of the corresponding positive number, then adding 1 to the
resulting bit pattern viewed as an unsigned integer. Biased representation: A fixed
value, called the bias, is added to the integer.
9.2 In sign-magnitude and twos complement, the left-most bit is a sign bit. In biased
representation, a number is negative if the value of the representation is less than
the bias.
9.3 Add additional bit positions to the left and fill in with the value of the original sign
bit.
9.4 Take the Boolean complement of each bit of the positive number, then adding 1 to
the resulting bit pattern viewed as an unsigned integer.
9.5 When the operation is performed on the n-bit integer –2n–1 (one followed by n – 1
zeros).
9.6 The twos complement representation of a number is the bit pattern used to
represent an integer. The twos complement of a number is the operation that
computes the negation of a number in twos complement representation.
9.7 The algorithm for performing twos complement addition involves simply adding
the two numbers in the same way as for ordinary addition for unsigned numbers,
with a test for overflow. For multiplication, if we treat the bit patterns as unsigned
numbers, their magnitude is different from the twos complement versions and so
the magnitude of the result will be different.
9.8 Sign, significand, exponent, base.
9.9 An advantage of biased representation is that nonnegative floating-point numbers
can be treated as integers for comparison purposes.
9.10 Positive overflow refers to integer representations and refers to a number that is
larger than can be represented in a given number of bits. Exponent overflow refers
to floating point representations and refers to a positive exponent that exceeds the
maximum possible exponent value. Significand overflow occurs when the
addition of two significands of the same sign result in a carry out of the most
significant bit.
9.11 1. Check for zeros. 2. Align the significands. 3. Add or subtract the significands.
4. Normalize the result.
9.12 To avoid unnecessary loss of the least significant bit.
9.13 Round to nearest: The result is rounded to the nearest representable number.
Round toward +∞: The result is rounded up toward plus infinity. Round toward
–∞: The result is rounded down toward negative infinity. Round toward 0: The
result is rounded toward zero.
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